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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
1 Gbit, 2 Gbit, 4 Gbit, 8 Gbit 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES - Up to 8 Gbit memory array - Up to 64Mbit spare area - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 1.8V device: VDD = 1.7 to 1.95V - 3.0V device: VDD = 2.7 to 3.6V PAGE SIZE - x8 device: (2048 + 64 spare) Bytes - x16 device: (1024 + 32 spare) Words BLOCK SIZE - x8 device: (128K + 4K spare) Bytes - x16 device: (64K + 2K spare) Words PAGE READ / PROGRAM - Random access: 25s (max) - Sequential access: 50ns (min) - Page program time: 300s (typ) COPY BACK PROGRAM MODE - Fast page copy without external buffering CACHE PROGRAM AND CACHE READ MODES - Internal Cache Register to improve the program and read throughputs FAST BLOCK ERASE - Block erase time: 2ms (typ) STATUS REGISTER ELECTRONIC SIGNATURE CHIP ENABLE `DON'T CARE' - for simple interface with microcontroller SERIAL NUMBER OPTION
Figure 1. Packages
TSOP48 12 x 20mm
FBGA
VFBGA63 9.5 x 12 x 1mm TFBGA63 9.5 x 12 x 1.2mm

DATA PROTECTION - Hardware and Software Block Locking - Hardware Program/Erase locked during Power transitions DATA INTEGRITY - 100,000 Program/Erase cycles - 10 years Data Retention RoHS COMPLIANCE - Lead-Free Components are Compliant with the RoHS Directive DEVELOPMENT TOOLS - Error Correction Code software and hardware models - Bad Blocks Management and Wear Leveling algorithms - PC Demo board with simulation software - File System OS Native reference software - Hardware simulation models
October 2005
1/57
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 1. Product List
Reference Part Number NAND01GR3B NAND01GW3B NAND01G-B NAND01GR4B NAND01GW4B NAND02GR3B NAND02GW3B NAND02G-B NAND02GR4B NAND02GW4B NAND04GR3B NAND04GW3B NAND04G-B NAND04GR4B NAND04GW4B NAND08GR3B NAND08GW3B NAND08G-B NAND08GR4B NAND08GW4B
Note: x16 organization only available for MCP
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TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Figure 2. Figure 3. Table 3. Figure 4. Figure 5. Figure 6. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP48 Connections, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FBGA63 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 11 FBGA63 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 12
MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Memory Array Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Enable (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-Up Read Enable, Lock/Unlock Enable (PRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Address Insertion, x8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Address Definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Table 9. Address Definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DEVICE OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 9. Random Data Output During Sequential Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10.Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Sequential Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12.Random Data Input During Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 11. Copy Back Program x8 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 12. Copy Back Program x16 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13.Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 14.Page Copy Back Program with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15.Cache Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Cache Program Error Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SR4, SR3 and SR2 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 14. Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 15. Electronic Signature Byte/Word 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Blocks Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Blocks Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 17.Blocks Unlock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Blocks Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Figure 18.Read Block Lock Status Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 16. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 19.Block Protection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SOFTWARE ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 17. Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 20.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 21.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 22.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Hardware Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 18. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 38 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 19. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 20. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 21. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 22. DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 23.Equivalent Testing Circuit for AC Characteristics Measurement. . . . . . . . . . . . . . . . . . . 40 Table 23. DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 24. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 25. AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 24.Command Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 25.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 26.Data Input Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 27.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 28.Read Status Register AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 29.Read Electronic Signature AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 30.Page Read Operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 31.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 32.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 33.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 34.Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 35.Ready/Busy Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 36.Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . 50
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Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 37.Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 38.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . 52 Table 26. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data . 52 Figure 39.VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . 53 Table 27. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data 53 Figure 40.TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . 54 Table 28. TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data 54 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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SUMMARY DESCRIPTION
The NAND Flash 2112 Byte/ 1056 Word Page is a family of non-volatile Flash memories that uses NAND cell technology. The devices range from 1 Gbit to 8 Gbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 2112 Bytes (2048 + 64 spare) or 1056 Words (1024 + 32 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). The devices have hardware and software security features: A Write Protect pin is available to give a hardware protection against program and erase operations. A Block Locking scheme is available to provide user code and/or data protection. The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Copy Back Program command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed. Each device has Cache Program and Cache Read features which improve the program and read throughputs for large files. During Cache Programming, the device loads the data in a Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array. During Cache Reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O Buffers to be read. All devices have the Chip Enable Don't Care feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation. All devices have the option of a Unique Identifier (serial number), which allows each device to be uniquely identified. The Unique Identifier options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest ST Sales office. The devices are available in the following packages: TSOP48 (12 x 20mm) for all products VFBGA63 (9.5 x 12 x 1mm, 0.8mm pitch) for 1Gb products TFBGA63 (9.5 x 12 x 1.2mm, 0.8mm pitch) for 2Gb Dual Die products For information on how to order these options refer to Table 29., Ordering Information Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to '1'. See Table 2., Product Description, for all the devices available in the family.
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Table 2. Product Description
Timings Reference Part Number Density Bus Width Page Size Block Size Memory Array Operating Voltage 1.7 to 1.95V 64 Pages x 2.7 to 3.6V 1024 Blocks 1.7 to 1.95V 2.7 to 3.6V 1.7 to 1.95V 64 Pages x 2.7 to 3.6V 2048 Blocks 1.7 to 1.95V 2.7 to 3.6V 1.7 to 1.95V 64 Pages x 2.7 to 3.6V 4096 Blocks 1.7 to 1.95V 2.7 to 3.6V 1.7 to 1.95V 64 Pages x 2.7 to 3.6V 8192 Blocks 1.7 to 1.95V 2.7 to 3.6V Random Access (max) 25s 25s 25s 25s 25s 25s 25s 25s 25s 25s 25s 25s 25s 25s 25s 25s Sequential Access (min) 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns Page Program (typ) 300s 300s 300s 300s 300s 300s 300s 300s 300s 300s 300s 300s 300s 300s 300s 300s 2ms TSOP48 2ms TSOP48 2ms TSOP48 TFBGA63(1) 2ms TSOP48 VFBGA63 Packages Block Erase (typ)
NAND01GR3B NAND01G-B NAND01GW3B NAND01GR4B NAND01GW4B NAND02GR3B NAND02G-B NAND02GW3B NAND02GR4B NAND02GW4B NAND04GR3B NAND04G-B NAND04GW3B NAND04GR4B NAND04GW4B NAND08GR3B NAND08G-B NAND08GW3B NAND08GR4B NAND08GW4B 8Gbit 4Gbit 2Gbit 1Gbit
x8 x16(2) x8 x16(2) x8
(2)
2048+64 128K+4K Bytes Bytes 1024+32 64K+2K Words Words 2048+64 128K+4K Bytes Bytes 1024+32 64K+2K Words Words 2048+64 128K+4K Bytes Bytes 1024+32 64K+2K Words Words 2048+64 128K+4K Bytes Bytes 1024+32 64K+2K Words Words
x16
x8 x16(2)
1. Dual Die devices only 2. x16 organization only available for MCP
Figure 2. Logic Block Diagram
Address Register/Counter AL CL W E WP R PRL X Decoder
Command Interface Logic
P/E/R Controller, High Voltage Generator
NAND Flash Memory Array
Page Buffer Command Register Cache Register Y Decoder
I/O Buffers & Latches
RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16
AI09373b
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Figure 3. Logic Diagram
VDD
I/O0-7
Table 3. Signal Names
I/O8-15 Data Input/Outputs for x16 devices Data Input/Outputs, Address Inputs, or Command Inputs for x8 and x16 devices Address Latch Enable Command Latch Enable Chip Enable Read Enable Ready/Busy (open-drain output) Write Enable Write Protect Power-Up Read Enable, Lock/Unlock Enable Supply Voltage Ground Not Connected Internally Do Not Use
E R W AL CL WP NAND Flash
I/O8-I/O15, x16
AL CL
I/O0-I/O7, x8/x16
E R
RB
RB W WP PRL
PRL
VDD VSS
VSS
AI09372b
NC DU
Note: x16 organization only available for MCP
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Figure 4. TSOP48 Connections, x8 devices
NC NC NC NC NC NC RB R E NC NC VDD VSS NC NC CL AL W WP NC NC NC NC NC
1
48
12 13
NAND Flash (x8)
37 36
NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC PRL VDD VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC
24
25
AI11750
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Figure 5. FBGA63 Connections, x8 devices (Top view through package)
1
2
3
4
5
6
7
8
9
10
A
DU
DU
DU
DU
B
DU
DU
DU
C
WP
AL
VSS
E
W
RB
D
NC
R
CL
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
NC
NC
NC
NC
NC
PRL
H
NC
I/O0
NC
NC
NC
VDD
J
NC
I/O1
NC
VDD
I/O5
I/O7
K
VSS
I/O2
I/O3
I/O4
I/O6
VSS
L
DU
DU
DU
DU
M
DU
DU
DU
DU
AI09376
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Figure 6. FBGA63 Connections, x16 devices (Top view through package)
1
2
3
4
5
6
7
8
9
10
A
DU
DU
DU
DU
B
DU
DU
DU
C
WP
AL
VSS
E
W
RB
D
NC
R
CL
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
NC
NC
NC
I/O5
I/O7
PRL
H
I/O8
I/O1
I/O10
I/O12
I/O14
VDD
J
I/O0
I/O9
I/O3
VDD
I/O6
I/O15
K
VSS
I/O2
I/O11
I/O4
I/O13
VSS
L
DU
DU
DU
DU
M
DU
DU
DU
DU
AI09377
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MEMORY ARRAY ORGANIZATION
The memory array is made up of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 64 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store Error correction Codes, software flags or Bad Block identification. In x8 devices the pages are split into a 2048 Byte main area and a spare area of 64 Bytes. In the x16 devices the pages are split into a 1,024 Word main area and a 32 Word spare area. Refer to Figure 7., Memory Array Organization. Bad Blocks The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device. The Bad Block Information is written prior to shipping (refer to Bad Block Management section for more details). Table 4. shows the minimum number of valid blocks in each device. The values shown include both the Bad Blocks that are present when the device is shipped and the Bad Blocks that could develop later on. These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes (refer to SOFTWARE ALGORITHMS section). Table 4. Valid Blocks
Density of Device 8 Gbits 4 Gbits 2 Gbits 1Gbit Min 8032 4016 2008 1004 Max 8192 4096 2048 1024
Figure 7. Memory Array Organization
x8 DEVICES
Block = 64 Pages Page = 2112 Bytes (2,048 + 64)
x16 DEVICES
Block = 64 Pages Page = 1056 Words (1024 + 32)
are Sp
a Are
Main Area Block Page
Main Area
are Sp
a Are
Block Page 8 bits 2048 Bytes 64 Bytes 1024 Words 32 Words 16 bits
Page Buffer, 2112 Bytes 2,048 Bytes
64 Bytes
Page Buffer, 1056 Words 8 bits 1,024 Words 32 Words 16 bits
AI09854
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SIGNAL DESCRIPTIONS
See Figure 3., Logic Diagram, and Table 3., Signal Names, for a brief overview of the signals connected to this device. Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/ O7 are left floating when the device is deselected or the outputs are disabled. Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data during a Read operation or input data during a Write operation. Command and Address Inputs only require I/O0 to I/O7. The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when the device is deselected or the outputs are disabled. Address Latch Enable (AL). The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When AL is high, the inputs are latched on the rising edge of Write Enable. Command Latch Enable (CL). The Command Latch Enable activates the latching of the Command inputs in the Command Interface. When CL is high, the inputs are latched on the rising edge of Write Enable. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, VIL, the device is selected. If Chip Enable goes high, vIH, while the device is busy, the device remains selected and does not go into standby mode. Read Enable (R). The Read Enable pin, R, controls the sequential data output during Read operations. Data is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal column address counter by one. Power-Up Read Enable, Lock/Unlock Enable (PRL). The Power-Up Read Enable, Lock/Unlock Enable input, PRL, is used to enable and disable the lock mechanism. When PRL is High, VIH, the device is in Block Lock mode. If the Power-Up Read Enable, Lock/Unlock Enable input is not required, the PRL pin should be left unconnected (Not Connected) or connected to VSS. Write Enable (W). The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 10s (min) is required before the Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time. Write Protect (WP). The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, VIL, the device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, V IL, during power-up and power-down. Ready/Busy (RB). The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R Controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes Ready/Busy goes High, VOH. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Refer to the Ready/Busy Signal Electrical Characteristics section for details on how to calculate the value of the pull-up resistor. VDD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V DD is below 2.5V (for 3V devices) or 1.5V (for 1.8V devices) to protect the device from any involuntary program/erase during power-transitions. Each device in a system should have VDD decoupled with a 0.1F capacitor. The PCB track widths should be sufficient to carry the required program and erase currents VSS Ground. Ground, VSS, is the reference for the power supply. It must be connected to the system ground.
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BUS OPERATIONS
There are six standard bus operations that control the memory. Each of these is described in this section, see Table 5., Bus Operations, for a summary. Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. Command Input Command Input bus operations are used to give commands to the memory. Commands are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. See Figure 24. and Table 24. for details of the timings requirements. Address Input Address Input bus operations are used to input the memory addresses. Four bus cycles are required to input the addresses for 1Gb devices whereas five bus cycles are required for the 2Gb, 4Gb and 8Gb devices (refer to Table 6. and Table 7., Address Insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses. See Figure 25. and Table 24. for details of the timings requirements. Data Input Data Input bus operations are used to input the data to be programmed. Table 5. Bus Operations
Bus Operation Command Input Address Input Data Input Data Output Write Protect Standby E VIL VIL VIL VIL X VIH AL VIL VIH VIL VIL X X CL VIH VIL VIL VIL X X R VIH VIH VIH Falling X X W Rising Rising Rising VIH X X WP X(2) X VIH X VIL VIL/VDD I/O0 - I/O7 Command Address Data Input Data Output X X I/O8 - I/O15(1) X X Data Input Data Output X X
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure 26. and Table 24. and Table 25. for details of the timings requirements. Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the lock status, the Electronic Signature and the Unique Identifier. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. See Figure 27. and Table 25. for details of the timings requirements. Write Protect Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. Standby When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power consumption is reduced.
Note: 1. Only for x16 devices. 2. WP must be VIH when issuing a program or erase command.
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Table 6. Address Insertion, x8 Devices
Bus Cycle 1st 2nd 3rd 4th 5th(2) I/O7 A7 VIL A19 A27 VIL I/O6 A6 VIL A18 A26 VIL I/O5 A5 VIL A17 A25 VIL I/O4 A4 VIL A16 A24 VIL I/O3 A3 A11 A15 A23 VIL I/O2 A2 A10 A14 A22 A30 I/O1 A1 A9 A13 A21 A29 I/O0 A0 A8 A12 A20 A28
Note: 1. Any additional address input cycles will be ignored. 2. The fifth cycle is valid for 2Gb, 4Gb and 8Gb devices. A28 is for 2Gb devices, A29-A28 are for 4Gb devices and A30-A28 for 8Gb devices only.
Table 7. Address Insertion, x16 Devices
Bus Cycle 1st 2nd 3rd 4th 5th(2) I/O8I/O15 X X X X X I/O7 A7 VIL A18 A26 VIL I/O6 A6 VIL A17 A25 VIL I/O5 A5 VIL A16 A24 VIL I/O4 A4 VIL A15 A23 VIL I/O3 A3 VIL A14 A22 VIL I/O2 A2 A10 A13 A21 A29 I/O1 A1 A9 A12 A20 A28 I/O0 A0 A8 A11 A19 A27
Note: 1. Any additional address input cycles will be ignored. 2. The fifth cycle is valid for 2Gb, 4Gb and 8Gb devices. A27 is for 2Gb devices, A28-A27 are for 4Gb devices and A29-A27 for 8Gb devices.
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Table 8. Address Definitions, x8
Address A0 - A11 A12 - A17 A18 - A27 A18 - A28 A18 - A29 A18 - A30 Block Address Block Address Block Address Block Address Definition Column Address Page Address 1Gb device 2Gb device 4Gb device 8Gb device
Table 9. Address Definitions, x16
Address A0 - A10 A11 - A16 A17 - A26 A17 - A27 A17 - A28 A17 - A29 Block Address Block Address Block Address Block Address Definition Column Address Page Address 1Gb device 2Gb device 4Gb device 8Gb device
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COMMAND SET
All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the ComTable 10. Commands
Bus Write Operations(1) Command 1st CYCLE Read Random Data Output Cache Read Exit Cache Read Page Program (Sequential Input default) Random Data Input Copy Back Program Cache Program Block Erase Reset Read Electronic Signature Read Status Register Read Block Lock Status Blocks Unlock Blocks Lock Blocks Lock-Down 00h(2) 05h 00h 34h 80h 85h 00h 80h 60h FFh 90h 70h 7Ah 23h 2Ah 2Ch 2nd CYCLE 30h E0h 31h - 10h - 35h 15h D0h - - - - 24h - - 3rd CYCLE - - - - - - 85h - - - - - - - - - 4th CYCLE - - - - - - 10h - - - - - - - - - Yes Yes Yes(3) Commands accepted during busy
mand Register. The two-step command sequences for program and erase operations are imposed to maximize data security. The Commands are summarized in Table 10., Commands.
Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. 2. For consecutive Read operations the 00h command does not need to be repeated. 3. Only during Cache Read busy.
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
DEVICE OPERATIONS
The following section gives the details of the device operations. Read Memory Array At Power-Up the device defaults to Read mode. To enter Read mode from another mode the Read command must be issued, see Table 10., Commands. Once a Read command is issued, subsequent consecutive Read commands only require the confirm command code (30h). Once a Read command is issued two types of operations are available: Random Read and Page Read. Random Read. Each time the Read command is issued the first read is Random Read. Page Read. After the first Random Read access, the page data (2112 Bytes or 1056 Words) is transferred to the Page Buffer in a time of tWHBH Figure 8. Read Operations (refer to Table 25. for value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal. The device can output random data in a page, instead of the consecutive sequential data, by issuing a Random Data Output command. The Random Data Output command can be used to skip some data during a sequential data output. The sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the Random Data Output command. The Random Data Output command can be issued as many times as required within a page. The Random Data Output command is not accepted during Cache Read operations.
CL
E
W
AL
R tBLBH1 RB
I/O
00h
Command Code
Address Input
30h
Command Code
Data Output (sequentially)
Busy ai08657b
Note: 1. Highest address depends on device density.
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 9. Random Data Output During Sequential Data Output
tBLBH1
(Read Busy time)
RB Busy
R
I/O
00h Cmd Code
Address Inputs
30h Cmd Code
Data Output
05h Cmd Code
Address Inputs
E0h Cmd Code
Data Output
5 Add cycles Row Add 1,2,3 Col Add 1,2 Spare Area
2Add cycles Col Add 1,2 Spare Area
Main Area
Main Area
ai08658
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Cache Read The Cache Read operation is used to improve the read throughput by reading data using the Cache Register. As soon as the user starts to read one page, the device automatically loads the next page into the Cache Register. An Cache Read operation consists of three steps (see Table 10.): 1. One bus cycle is required to setup the Cache Read command (the same as the standard Read command) 2. Four or Five (refer to Table 6. and Table 7.) bus cycles are then required to input the Start Address 3. One bus cycle is required to issue the Cache Read confirm command to start the P/E/R Controller. The Start Address must be at the beginning of a page (Column Address = 00h, see Table 8. and Table 9.). This allows the data to be output uninterrupted after the latency time (tBLBH1), see Figure 10. The Ready/Busy signal can be used to monitor the start of the operation. During the latency period the Ready/Busy signal goes Low, after this the Ready/ Busy signal goes High, even if the device is internally downloading page n+1. Once the Cache Read operation has started, the Status Register can be read using the Read Status Register command. During the operation, SR5 can be read, to find out whether the internal reading is ongoing (SR5 = `0'), or has completed (SR5 = `1'), while SR6 indicates whether the Cache Register is ready to download new data. To exit the Cache Read operation an Exit Cache Read command must be issued (see Table 10.). If the Exit Cache Read command is issued while the device is internally reading page n+1, page n will still be output, but not page n+1.
Figure 10. Cache Read Operation
(Read Busy time)
tBLBH1
RB Busy I/O
00h
Address Inputs
31h
1st page
2nd page
3rd page
last page
34h
Read Setup Code
Cache Read Confirm Code
Block N Data Output
Exit Cache Read Code
ai08661
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Page Program The Page Program operation is the standard operation to program data to the memory array. Generally, data is programmed sequentially, however the device does support Random Input within a page. The memory array is programmed by page, however partial page programming is allowed where any number of Bytes (1 to 2112) or Words (1 to 1056) can be programmed. The maximum number of consecutive partial page program operations allowed in the same page is eight. After exceeding this a Block Erase command must be issued before any further program operations can take place in that page. Sequential Input. To input data sequentially the addresses must be sequential and remain in one block. For Sequential Input each Page Program operation consists of five steps (see Figure 11.): 1. one bus cycle is required to setup the Page Program (Sequential Input) command (see Table 10.) 2. four or five bus cycles are then required to input the program address (refer to Table 6. and Table 7.) 3. the data is then loaded into the Data Registers 4. one bus cycle is required to issue the Page Program confirm command to start the P/E/R Controller. The P/E/R will only start if the data has been loaded in step 3. Figure 11. Page Program Operation
tBLBH2
5. the P/E/R Controller then programs the data into the array. Random Data Input. During a Sequential Input operation, the next sequential address to be programmed can be replaced by a random address, by issuing a Random Data Input command. The following two steps are required to issue the command: 1. one bus cycle is required to setup the Random Data Input command (see Table 10.) 2. two bus cycles are then required to input the new column address (refer to Table 6.) Random Data Input can be repeated as often as required in any given page. Once the program operation has started the Status Register can be read using the Read Status Register command. During program operations the Status Register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. During the program operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the P/ E/R Controller bit SR6 is set to `1' and the Ready/ Busy signal goes High. The device remains in Read Status Register mode until another valid command is written to the Command Interface.
(Program Busy time)
RB Busy I/O 80h Page Program Setup Code Address Inputs Data Input 10h Confirm Code 70h SR0
Read Status Register
ai08659
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Figure 12. Random Data Input During Sequential Data Input
(Program Busy time)
tBLBH2
RB Busy I/O 80h Cmd Code Address Inputs Data Intput 85h Cmd Code Address Inputs 2 Add cycles Col Add 1,2 Data Input 10h Confirm Code 70h SR0
Read Status Register
5 Add cycles Row Add 1,2,3 Col Add 1,2
Main Area
Spare Area
Main Area
Spare Area
ai08664
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. If the Copy Back Program operation fails an error is signalled in the Status Register. However as the standard external ECC cannot be used with the Copy Back Program operation bit error due to charge loss cannot be detected. For this reason it is recommended to limit the number of Copy Back Program operations on the same data and or to improve the performance of the ECC. The Copy Back Program operation requires four steps: 1. The first step reads the source page. The operation copies all 1056 Words/ 2112 Bytes from the page into the Data Buffer. It requires: - - - one bus write cycle to setup the command 4 bus write cycles to input the source page address one bus write cycle to issue the confirm command code Table 12. Copy Back Program x16 Addresses
Density 1 Gbit 2 Gbit 2 Gbit DD(1) 4 Gbit
Note: 1. DD = Dual Die
11. for the addresses that must be the same for the Source and Target pages. 3. Then the confirm command is issued to start the P/E/R Controller. To see the Data Input cycle for modifying the source page and an example of the Copy Back Program operation refer to Figure 13. . A data input cycle to modify a portion or a multiple distant portion of the source page, is shown in Figure 14. Table 11. Copy Back Program x8 Addresses
Density 1 Gbit 2 Gbit 2 Gbit DD(1) 4 Gbit
Note: 1. DD = Dual Die
Same Address for Source and Target Pages no constraint no constraint A28 no constraint
Same Address for Source and Target Pages no constraint A28 A27 no constrain
2. When the device returns to the ready state (Ready/Busy High), the next bus write cycle of the command is given with the 4 bus cycles to input the target page address. Refer to Table
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Figure 13. Copy Back Program
I/O
00h Read Code
Source Add Inputs
35h
85h Copy Back Code
Target Add Inputs
10h
70h
SR0
Read Status Register tBLBH2
(Program Busy time)
tBLBH1
(Read Busy time)
RB Busy Busy
ai09858b
Note: Copy back program is only permitted between odd address pages or even address pages.
Figure 14. Page Copy Back Program with Random Data Input
I/O
00h Read Code
Source Add Inputs 35h
85h Copy Back Code
Target Add Inputs
Data
85h
2 Cycle Add Inputs
Data
10h
70h
SR0
Unlimited number of repetitions
tBLBH1
(Read Busy time)
tBLBH2
(Program Busy time)
RB Busy Busy
ai11001
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Cache Program The Cache Program operation is used to improve the programming throughput by programming data using the Cache Register. The Cache Program operation can only be used within one block. The Cache Register allows new data to be input while the previous data that was transferred to the Page Buffer is programmed into the memory array. Each Cache Program operation consists of five steps (refer to Figure 15.): 1. First of all the program setup command is issued (one bus cycle to issue the program setup command then four bus write cycles to input the address), the data is then input (up to 2112 Bytes/ 1056 Words) and loaded into the Cache Register. 2. One bus cycle is required to issue the confirm command to start the P/E/R Controller. 3. The P/E/R Controller then transfers the data to the Page Buffer. During this the device is busy for a time of tWHBH2. 4. Once the data is loaded into the Page Buffer the P/E/R Controller programs the data into the memory array. As soon as the Cache Registers are empty (after tWHBH2) a new Figure 15. Cache Program Operation
tBLBH5 tBLBH5 tCACHEPG
Cache program command can be issued, while the internal programming is still executing. Once the program operation has started the Status Register can be read using the Read Status Register command. During Cache Program operations SR5 can be read to find out whether the internal programming is ongoing (SR5 = `0') or has completed (SR5 = `1') while SR6 indicates whether the Cache Register is ready to accept new data. If any errors have been detected on the previous page (Page N-1), the Cache Program Error Bit SR1 will be set to `1', while if the error has been detected on Page N the Error Bit SR0 will be set to '1'. When the next page (Page N) of data is input with the Cache Program command, tWHBH2 is affected by the pending internal programming. The data will only be transferred from the Cache Register to the Page Buffer when the pending program cycle is finished and the Page Buffer is available. If the system monitors the progress of the operation using only the Ready/Busy signal, the last page of data must be programmed with the Page Program confirm command (10h). If the Cache Program confirm command (15h) is used instead, Status Register bit SR5 must be polled to find out if the last programming is finished before starting any other operations.
(Cache Busy time)
RB Busy I/O
80h
Busy
80h
Busy
80h
Address Inputs
Data Inputs
15h
Address Inputs
Data Inputs
15h
Address Inputs
Data Inputs
10h
70h SR0
Page Program Code First Page
Cache Program Code
Page Program Code
Cache Program Confirm Code Second Page Last Page
Read Status Page Register Program Confirm Code
(can be repeated up to 63 times) ai08672
Note: 1. Up to 64 pages can be programmed in one Cache Program operation. 2. tCACHEPG is the program time for the last page + the program time for the (last - 1)th page - (Program command cycle time + Last page data loading time).
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Block Erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to `1'. All previous data in the block is lost. An erase operation consists of three steps (refer to Figure 16.): 1. One bus cycle is required to setup the Block Erase command. Only addresses A18-A27 (x8) or A17-A26 (x16) are used, the other address inputs are ignored. 2. two or three bus cycles are then required to load the address of the block to be erased. Refer to Table 8. and Table 9. for the block addresses of each device. Figure 16. Block Erase Operation
tBLBH3
(Erase Busy time)
3. one bus cycle is required to issue the Block Erase confirm command to start the P/E/R Controller. The operation is initiated on the rising edge of write Enable, W, after the confirm command is issued. The P/E/R Controller handles Block Erase and implements the verify process. During the Block Erase operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the P/ E/R Controller bit SR6 is set to `1' and the Ready/ Busy signal goes High. If the operation completed successfully, the Write Status Bit SR0 is `0', otherwise it is set to `1'.
RB Busy I/O 60h Block Erase Setup Code Block Address Inputs D0h Confirm Code 70h SR0
Read Status Register
ai07593
Reset The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued during any operation, the operation will be aborted. If it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. If the device has already been reset then the new Reset command will not be accepted. The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value of tBLBH4 depends on the operation that the device was performing when the command was issued, refer to Table 25. for the values.
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Read Status Register The device contains a Status Register which provides information on the current or previous Program or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command. The Status Register information is present on the output data bus (I/O0I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the Status Register. After the Read Status Register command has been issued, the device remains in Read Status Register mode until another command is issued. Therefore if a Read Status Register command is issued during a Random Read cycle a new Read command must be issued to continue with a Page Read operation. The Status Register bits are summarized in Table 13., Status Register Bits, . Refer to Table 13. in conjunction with the following text descriptions. Write Protection Bit (SR7). The Write Protection bit can be used to identify if the device is protected or not. If the Write Protection bit is set to `1' the device is not protected and program or erase operations are allowed. If the Write Protection bit is set to `0' the device is protected and program or erase operations are not allowed. P/E/R Controller and Cache Ready/Busy Bit (SR6). Status Register bit SR6 has two different functions depending on the current operation. During Cache Program operations SR6 acts as a Cache Program Ready/Busy bit, which indicates whether the Cache Register is ready to accept new data. When SR6 is set to '0', the Cache Register is busy and when SR6 is set to '1', the Cache Register is ready to accept new data. During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to `0', the P/E/R Controller is active (device is busy); when the bit is set to `1', the P/E/R Controller is inactive (device is ready). P/E/R Controller Bit (SR5). The Program/Erase/ Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to `0', the P/E/R Controller is active (device is busy); when the bit is set to `1', the P/E/R Controller is inactive (device is ready). Cache Program Error Bit (SR1). The Cache Program Error bit can be used to identify if the previous page (page N-1) has been successfully programed or not in a Cache Program operation. SR1 is set to '1' when the Cache Program operation has failed to program the previous page (page N1) correctly. If SR1 is set to `0' the operation has completed successfully. The Cache Program Error bit is only valid during Cache Program operations, during other operations it is Don't Care. Error Bit (SR0). The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to '1' when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to `0' the operation has completed successfully. The Error Bit SR0, in a Cache Program operation, indicates a failure on Page N. SR4, SR3 and SR2 are Reserved.
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Table 13. Status Register Bits
Bit SR7 Name Write Protection '0' Program/ Erase/ Read Controller SR6(1) Cache Ready/Busy '0' SR5 SR4, SR3, SR2 SR1 Program/ Erase/ Read Controller(2) Reserved Cache Program Error(3) '1' '0' Don't Care '1' '0' `1' Generic Error SR0(1) Cache Program Error `0' Page N programmed successfully
Note: 1. The SR6 bit and SR0 bit have a different meaning during Cache Program and Cache Read operations. 2. Only valid for Cache Program operations, for other operations it is same as SR6. 3. Only valid for Cache Program operations, for other operations it is Don't Care.
Logic Level '1' Not Protected Protected
Definition
'1' '0' '1'
P/E/R C inactive, device ready P/E/R C active, device busy Cache Register ready (Cache Program only) Cache Register busy (Cache Program only) P/E/R C inactive, device ready P/E/R C active, device busy
Page N-1 failed in Cache Program operation Page N-1 programmed successfully Error - operation failed No Error - operation successful Page N failed in Cache Program operation
`0' `1'
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Read Electronic Signature The device contains a Manufacturer Code and Device Code. To read these codes three steps are required: 1. one Bus Write cycle to issue the Read Electronic Signature command (90h) Table 14. Electronic Signature
Byte/Word 1 Part Number Manufacturer Code NAND01GR3B 20h NAND01GW3B NAND01GR4B 0020h NAND01GW4B NAND02GR3B 20h NAND02GW3B NAND02GR4B 0020h NAND02GW4B NAND04GR3B 20h NAND04GW3B NAND04GR4B 0020h NAND04GW4B NAND08GR3B 20h NAND08GW3B NAND08GR4B 0020h NAND08GW4B C3h D3h B3h CCh A3h DCh BCh CAh ACh Reserved 80h DAh BAh Page Size Spare Area size Sequential Access Time Block Size Organization (seeTable 15.) C1h AAh F1h B1h Device code A1h Byte/Word 2 Byte/Word 3 Byte/Word 4
2. one Bus Write cycle to input the address (00h) 3. four Bus Read Cycles to sequentially output the data (as shown in Table 14., Electronic Signature).
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Table 15. Electronic Signature Byte/Word 4
I/O Definition Page Size (Without Spare Area) Spare Area Size (Byte / 512 Byte) Sequential Access Time Value 00 01 10 11 0 1 0 1 00 01 10 11 0 1 Reserved Description 1K 2K Reserved Reserved 8 16 Standard (50 ns) Fast (30 ns) 64K 128K 256K Reserved X8 X16
I/O1-I/O0
I/O2 I/O3
I/O5-I/O4
Block Size (Without Spare Area)
I/O6 I/O7
Organization Not Used
Note: 1. VDDth is equal to 2.5V for 3V Power Supply devices and to 1.5V for 1.8V Power Supply devices.
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DATA PROTECTION
The device has both hardware and software features to protect against program and erase operations. It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations. It is recommended to keep WP at VIL during power-up and power-down. In addition, to protect the memory from any involuntary program/erase operations during powertransitions, the device has an internal voltage detector which disables all functions whenever V CC is below 1.5V. The device features a Block Lock mode, which is enabled by setting the Power-Up Read Enable, Lock/Unlock Enable, PRL, signal to High. The Block Lock mode has two levels of software protection. Blocks Lock/Unlock
Refer to Figure 24., Command Latch AC Waveforms for details on how to issue the command. Blocks Unlock A sequence of consecutive locked blocks can be unlocked, to allow program or erase operations, by issuing an Blocks Unlock command (see Table 10.). The Blocks Unlock command consists of four steps: One bus cycle to setup the command
two or three bus cycles to give the Start Block Address (refer to Table 8. , Table 9. and Figure 17.) one bus cycle to confirm the command two or three bus cycles to give the End Block Address (refer to Table 8. , Table 9.and Figure 17.).

Blocks Lock-down
Refer to Figure 19. for an overview of the protection mechanism. Blocks Lock All the blocks are locked simultaneously by issuing a Blocks Lock command (see Table 10.). All blocks are locked after power-up and when the Write Protect signal is Low. Once all the blocks are locked, one sequence of consecutive blocks can be unlocked by using the Blocks Unlock command. Figure 17. Blocks Unlock Operation
The Start Block Address must be nearer the logical LSB (Least Significant Bit) than End Block Address. If the Start Block Address is the same as the End Block Address, only one block is unlocked. Only one consecutive area of blocks can be unlocked at any one time. It is not possible to unlock multiple areas.
WP
I/O
23h Blocks Unlock Command
Add1
Add2
Add3
24h
Add1
Add2
Add3
Start Block Address, 3 cycles
End Block Address, 3 cycles
ai08670
Note: Three address cycles are required for 2,4 and 8 Gb devices. 1Gb devices only require two address cycles.
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Blocks Lock-Down The Lock-Down feature provides an additional level of protection. A Locked-down block cannot be unlocked by a software command. Locked-Down blocks can only be unlocked by setting the Write Protect signal to Low for a minimum of 100ns. Only locked blocks can be locked-down. The command has no affect on unlocked blocks. Refer to Figure 24., Command Latch AC Waveforms for details on how to issue the command. Block Lock Status In Block Lock mode (PRL High) the Block Lock Status of each block can be checked by issuing a Figure 18. Read Block Lock Status Operation Read Block Lock Status command (see Table 10.). The command consists of: one bus cycle to give the command code three bus cysles to give the block address After this, a read cycle will then output the Block Lock Status on the I/O pins on the falling edge of Chip Enable or Read Enable, whichever occurs last. Chip Enable or Read Enable do not need to be toggled to update the status. The Read Block Lock Status command will not be accepted while the device is busy (RB Low). The device will remain in Read Block Lock Status mode until another command is issued.
W tWHRL R
I/O
7Ah Read Block Lock Status Command
Add1
Add2
Add3
Dout Block Lock Status
Block Address, 3 cycles
ai08669
Note: Three address cycles are required for 2,4 and 8 Gb devices. 1Gb devices only require two address cycles.
Table 16. Block Lock Status
Status Locked Unlocked Locked-Down Unlocked in LockedDown Area
Note: X = Don't Care.
I/O7-I/O3 X X X X
I/O2 0 1 0 1
I/O1 1 1 0 0
I/O0 0 0 1 1
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Figure 19. Block Protection State Diagram
Power-Up
Block Unlock Command (start + end block address)
Locked
Blocks Lock-Down Command
Blocks Lock Command WP VIL >100ns Unlocked in Locked Area WP VIL >100ns
WP VIL >100ns
Locked-Down
Blocks Lock-Down Command
Unlocked in Locked-Down Area
AI08663c
Note: PRL must be High for the software commands to be accepted.
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SOFTWARE ALGORITHMS
This section gives information on the software algorithms that ST recommends to implement to manage the Bad Blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. For this reason, the number of program and erase cycles is limited (see Table 18. for value) and it is recommended to implement Garbage Collection, a Wear-Leveling Algorithm and an Error Correction Code, to extend the number of program and erase cycles and increase the data retention. To help integrate a NAND memory into an application ST Microelectronics can provide: A Demo board with NAND simulation software for PCs
These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See the "Copy Back Program" section for more details. Refer to Table 17. for the recommended procedure to follow if an error occurs during an operation. Table 17. Block Failure
Operation Erase Program Read Recommended Procedure Block Replacement Block Replacement or ECC ECC
File System OS Native reference software, which supports the basic commands of file management.
Contact the nearest ST Microelectronics sales office for more details. Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block, where the 1st and 6th Bytes, or 1st Word, in the spare area of the 1st page, does not contain FFh, is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 20. Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block.
Figure 20. Bad Block Management Flowchart
START
Block Address = Block 0
Increment Block Address Update Bad Block table
Data = FFh? YES
NO
Last block? YES
NO
END
AI07588C
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 21. Garbage Collection
Old Area New Area (After GC)
Valid Page Invalid Page Free Page (Erased)
AI07599B
Garbage Collection When a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a Garbage Collection algorithm. In a Garbage Collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 21.). Wear-leveling Algorithm For write-intensive applications, it is recommended to implement a Wear-leveling Algorithm to monitor and spread the number of write cycles per block. In memories that do not use a Wear-Leveling Algorithm not all blocks get used at the same rate. Blocks with long-lived data do not endure as many write cycles as the blocks with frequently-changed data. The Wear-leveling Algorithm ensures that equal use is made of all the available write cycles for each block. There are two wear-leveling levels: First Level Wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles
imum number of write cycles per block reaches a specific threshold. Error Correction Code An Error Correction Code (ECC) can be implemented in the Nand Flash memories to identify and correct errors in the data. For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for line parity plus 6 bits for column parity). An ECC model is available in VHDL or Verilog. Contact the nearest ST Microelectronics sales office for more details. Figure 22. Error Detection
New ECC generated during read
XOR previous ECC with new ECC
All results = zero? YES 22 bit data = 0
NO
>1 bit = zero? YES 11 bit data = 1
NO
Second Level Wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequentlychanged data.
1 bit data = 1
No Error
Correctable Error
ECC Error
The Second Level Wear-leveling is triggered when the difference between the maximum and the minai08332
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Hardware Simulation Models Behavioral simulation models. Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hardware. IBIS simulations models. IBIS (I/O Buffer Information Specification) models describe the behavior of the I/O buffers and electrical characteristics of Flash devices. These models provide information such as AC characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connections and can be used to resolve compatibility issues when upgrading devices. They can be imported into SPICETOOLS.
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PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 18. Table 18. Program, Erase Times and Program Erase Endurance Cycles
NAND Flash Parameters Min Page Program Time Block Erase Time Program/Erase Cycles (per block) Data Retention 100,000 10 Typ 300 2 Max 700 3 s ms cycles years Unit
MAXIMUM RATING
Stressing the device above the ratings listed in Table 19., Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 19. Absolute Maximum Ratings
Value Symbol TBIAS TSTG TLEAD VIO (1) Parameter Min Temperature Under Bias Storage Temperature Lead temperature during soldering (2) 1.8V devices Input or Output Voltage 3 V devices 1.8V devices Supply Voltage 3 V devices - 0.6 4.6 V - 0.6 - 0.6 4.6 2.7 V V - 0.6 - 50 - 65 Max 125 150 260 2.7 C C C V Unit
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
VDD
Note: 1. Minimum Voltage may undershoot to -2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may overshoot to V DD + 2V for less than 20ns during transitions on I/O pins. 2. Compatibility with Lead-free soldering processes in accordance with ECOPACK 7191395 specifications. Not exceeding 250C for more than 10s, and peaking at 260C.
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 20., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 20. Operating and AC Measurement Conditions
NAND Flash Parameter Min 1.8V devices Supply Voltage (VDD) 3V devices Grade 1 Grade 6 1.8V devices Load Capacitance (CL) (1 TTL GATE and CL) 3V devices (2.7 - 3.6V) 1.8V devices Input Pulses Voltages 3V devices 1.8V devices Input and Output Timing Ref. Voltages 3V devices Output Circuit Resistor Rref Input Rise and Fall Times 1.5 8.35 5 V k ns 0.4 0.9 2.4 V V 0 50 VDD pF V 1.7 2.7 0 -40 30 Max 1.95 3.6 70 85 V V C C pF Units
Ambient Temperature (TA)
Table 21. Capacitance
Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance(2) Test Condition VIN = 0V VIL = 0V Typ Max 10 10 Unit pF pF
Note: 1. TA = 25C, f = 1 MHz. CIN and CI/O are not 100% tested 2. input/output capacitances double in stacked devices
Table 22. DC Characteristics, 1.8V Devices
Symbol IDD1 IDD2 IDD3 IDD5 ILI ILO VIH Operating Current Parameter Sequential Read Program Erase Standby Current (CMOS)(1) Input Leakage Current(1) Output Leakage Current(1) Input High Voltage Test Conditions tRLRL minimum E=VIL, IOUT = 0 mA E=VDD-0.2, WP=0/VDD VIN= 0 to VDDmax VOUT = 0 to VDDmax Min VDD-0.4 Typ 8 8 8 10 Max 15 15 15 50 10 10 VDD+0.3 Unit mA mA mA A A A V
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Symbol VIL VOH VOL IOL (RB) VLKO Parameter Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (RB) VDD Supply Voltage (Erase and Program lockout) Test Conditions IOH = -100A IOL = 100A VOL = 0.1V Min -0.3 VDD-0.1 3 Typ 4 1.1 Max 0.4 0.1 Unit V V V mA V
Note: 1. leakage current and standby current double in stacked devices
Figure 23. Equivalent Testing Circuit for AC Characteristics Measurement
VDD
2Rref
NAND Flash
CL
2Rref
GND
GND
Ai11085
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 23. DC Characteristics, 3V Devices
Symbol IDD1 IDD2 IDD3 Operating Current Parameter Sequential Read Program Erase Standby current (TTL)(1) Standby Current (CMOS)(1) Input Leakage Current(1) Output Leakage Current(1) Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (RB) VDD Supply Voltage (Erase and Program lockout) Test Conditions tRLRL minimum E=VIL, IOUT = 0 mA E=VIH, WP=0/VDD E=VDD-0.2, WP=0/VDD VIN= 0 to VDDmax VOUT = 0 to VDDmax IOH = -400A IOL = 2.1mA VOL = 0.4V VDD+0.8 -0.3 2.4 8 10 10 1.7 Min Typ 15 15 15 Max 30 30 30 1 50 10 10 VDD+0.3 VDD+0.2 0.4 Unit mA mA mA mA A A A V V V V mA V
IDD4
IDD5 ILI ILO VIH VIL VOH VOL IOL (RB) VLKO
Note: 1. leakage current and standby current double in stacked devices
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Table 24. AC Characteristics for Command, Address, Data Input
Symbol tALLWL tALHWL tCLHWL tCLLWL tDVWH tELWL tWHALH tWHCLH tWHCLL tWHDX tWHEH tWHWL tWLWH tWLWL tCLH Write Enable High to Command Latch Low tDH tCH tWH tWP tWC Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Enable Low to Write Enable Low Data Hold time E Hold time W High Hold time W Pulse Width Write Cycle time Min Min Min Min Min 10 10 20 25(1) 60 10 10 20 25(1) 50 ns ns ns ns ns tDS tCS tALH Alt. Symbol tALS Address Latch High to Write Enable Low Command Latch High to Write Enable Low tCLS Command Latch Low to Write Enable Low Data Valid to Write Enable High Chip Enable Low to Write Enable Low Write Enable High to Address Latch High Write Enable High to Command Latch High CL hold time Min 10 10 ns Data Setup time E Setup time AL Hold time Min Min Min 20 0 10 20 0 10 ns ns ns CL Setup time Min 0 0 ns Parameter Address Latch Low to Write Enable Low AL Setup time Min 0 0 ns 1.8V Devices 3V Unit Devices
Note: 1. If tELWL is less than 10ns, tWLWH must be minimum 35ns, otherwise, tWLWH may be minimum 25ns.
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Table 25. AC Characteristics for Operations
Symbol tALLRL1 tALLRL2 tBHRL tBLBH1 tBLBH2 tBLBH3 tBLBH4 tBLBH5 tCBSY tPROG tBERS Ready/Busy Low to Ready/Busy High Alt. Symbol tAR tRR Address Latch Low to Read Enable Low Parameter Read Electronic Signature Read cycle Min Min Min Max Max Max Max Typ Max Max Max Max Min Min Max Max Min Min Min Min Max 1.8V Devices 10 10 20 25 700 3 5 3 700 5 10 500 10 0 20 45 20 15 25 60 35 3V Unit Devices 10 10 20 25 700 3 5 3 700 5 10 500 10 0 20 45 20 15 25 50 35 ns ns ns s s ms s s s s s s ns ns ns ns ns ns ns ns ns
Ready/Busy High to Read Enable Low Read Busy time Program Busy time Erase Busy time Reset Busy time, during ready Cache Busy time Reset Busy time, during read
tWHBH1
tRST
Write Enable High to Ready/Busy High
Reset Busy time, during program Reset Busy time, during erase
tCLLRL tDZRL tEHQZ tELQV tRHRL TEHQX TRHQX tRLRH tRLRL tRLQV tWHBH tWHBL tWHRL tWLWL
tCLR tIR tCHZ tCEA tREH TOH tRP tRC tREA tR tWB tWHR tWC
Command Latch Low to Read Enable Low Data Hi-Z to Read Enable Low Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Read Enable High to Read Enable Low Read Enable High Hold time
Chip Enable high or Read Enable high to Output Hold Read Enable Low to Read Enable High Read Enable Low to Read Enable Low Read Enable Low to Output Valid Write Enable High to Ready/Busy High Read Enable Pulse Width Read Cycle time Read Enable Access time Read ES Access time(3) Read Busy time
Max Max Min Min
25 100 60 60
25 100 60 50
s ns ns ns
Write Enable High to Ready/Busy Low Write Enable High to Read Enable Low Write Enable Low to Write Enable Low Write Cycle time
Note: 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 34, 35 and 36. 2. To break the sequential read cycle, E must be held High for longer than tEHEL. 3. ES = Electronic Signature.
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 24. Command Latch AC Waveforms
CL tCLHWL
(CL Setup time)
tWHCLL
(CL Hold time)
tELWL
(E Setup time)
tWHEH
(E Hold time)
E tWLWH W tALLWL
(ALSetup time)
tWHALH
(AL Hold time)
AL tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
I/O
Command
ai08028
Figure 25. Address Latch AC Waveforms
(CL Setup time)
tCLLWL
CL tELWL tWLWL tWLWL tWLWL
(E Setup time)
E tWLWH W tALHWL
(AL Setup time)
tWLWH
tWLWH
tWLWH
tWHWL tWHALL
(AL Hold time)
tWHWL tWHALL
tWHWL tWHALL
AL tDVWH tDVWH tWHDX
(Data Hold time)
(Data Setup time)
tDVWH tWHDX Adrress cycle 2 Adrress cycle 3
tDVWH tWHDX Adrress cycle 4 tWHDX
I/O
Adrress cycle 1
ai08029
Note: A fifth address cycle is required for 2Gb, 4Gb and 8Gb devices.
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 26. Data Input Latch AC Waveforms
tWHCLH
(CL Hold time)
CL tWHEH
(E Hold time)
E
(ALSetup time)
tALLWL
tWLWL
AL tWLWH W tDVWH
(Data Setup time)
tWLWH
tWLWH
tDVWH tWHDX
(Data Hold time)
tDVWH tWHDX tWHDX
I/O
Data In 0
Data In 1
Data In Last
ai08030
Note: Data In Last is 2112 in x8 devices and 1056 in x16 devices.
Figure 27. Sequential Data Output after Read AC Waveforms
tRLRL
(Read Cycle time)
E tRHRL
(R High Holdtime)
tEHQZ
R tRHQZ tRLQV
(R Accesstime)
tRHQZ tRLQV
tRLQV
I/O tBHRL RB
Data Out
Data Out
Data Out
ai08031
Note: 1. CL = Low, AL = Low, W = High.
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 28. Read Status Register AC Waveform
tCLLRL CL tWHCLL tCLHWL E tELWL W tWHRL R tDZRL tDVWH
(Data Setup time)
tWHEH
tWLWH tELQV tEHQZ
tWHDX
(Data Hold time)
tRLQV
tRHQZ
I/O
70h/ 72h/ 73h/ 74h/ 75h
Status Register Output
ai08666
Figure 29. Read Electronic Signature AC Waveform
CL
E
W
AL tALLRL1
R
(Read ES Access time)
tRLQV
I/O
90h Read Electronic Signature Command
00h 1st Cycle Address
Byte1 Man. code
Byte2 Device code
Byte3 00h
Byte4 see Note.1
ai08667
Note: 1. Refer to Table 14. for the values of the Manufacturer and Device Codes, and to Table 15. for the information contained in Byte4.
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 30. Page Read Operation AC Waveform
CL tEHEL E tWLWL W tWHBL AL tALLRL2 tWHBH tRLRL
(Read Cycle time)
tEHQZ
tEHBH
tRHQZ
R tRLRH tBLBH1 RB tRHBL
I/O
00h
Add.N cycle 1
Add.N cycle 2
Add.N cycle 3
Add.N cycle 4
30h
Data N
Data N+1
Data N+2
Data Last
Command Code
Address N Input
Busy
Data Output from Address N to Last Byte or Word in Page
ai08660
Note: A fifth address cycle is required for 2Gb, 4Gb and 8Gb devices.
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 31. Page Program AC Waveform
CL
E tWLWL
(Write Cycle time)
tWLWL
tWLWL
W tWHBL tBLBH2
(Program Busy time)
AL
R
I/O
80h
Add.N cycle 1
Add.N Add.N Add.N cycle 2 cycle 3 cycle 4
N
Last
10h
70h
SR0
RB Page Program Setup Code Confirm Code
Address Input
Data Input
Page Program Read Status Register
ai08668
Note: A fifth address cycle is required for 2Gb, 4Gb and 8Gb devices.
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Figure 32. Block Erase AC Waveform
CL
E tWLWL
(Write Cycle time)
W tWHBL AL
(Erase Busy time)
tBLBH3
R
I/O
60h
Add. Add. Add. cycle 1 cycle 2 cycle 3
D0h
70h
SR0
RB Block Erase Setup Command Confirm Code Block Erase Read Status Register
ai08038b
Block Address Input
Note: Address cycle 3 is required for 2Gb, 4Gb and 8Gb devices only.
Figure 33. Reset AC Waveform
W
AL CL
R I/O FFh tBLBH4
(Reset Busy time)
RB
ai08043
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Ready/Busy Signal Electrical Characteristics Figures 35, 34 and 36 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor R P can be calculated using the following equation: Figure 35. Ready/Busy Load Circuit
(V - ) DDmax V OLmax R P min = ----------------------------------------------------------I OL + I L
So,
VDD RP
ibusy
1.85V R P min ( 1.8V ) = --------------------------+ 3mA IL 3.2V R P min ( 3V ) = --------------------------8mA + I L
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. R P max is determined by the maximum value of tr. Figure 34. Ready/Busy AC Waveform
ready VDD VOH VOL busy tf tr
AI07564B
DEVICE RB Open Drain Output
VSS
AI07563B
Figure 36. Resistor Value Versus Waveform Timings For Ready/Busy Signal
VDD = 1.8V, CL = 30pF 400 4 400
VDD = 3.3V, CL = 100pF 4
400
300 tr, tf (ns)
3 ibusy (mA) tr, tf (ns)
300
2.4
300
3 ibusy (mA)
ai07565B
200
1.7
2
200
200
2
120
1.2
100
30 1.7
0.85 60 1.7
90 0.57 1.7
1
0.43 1.7
100
100 3.6 3.6
0.8
1
0.6
0
0
3.6
3.6
1
2 RP (K)
3
4
1
2 RP (K)
3
4
tf
tr
ibusy
Note: T = 25C.
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Data Protection The ST NAND device is designed to guarantee Data Protection during Power Transitions. A VDD detection circuit disables all NAND operations, if V DD is below the VLKO threshold. Figure 37. Data Protection In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept low (VIL) to guarantee hardware protection during power transitions as shown in the below figure.
VDD
Nominal Range
VLKO
Locked
Locked
W
Ai11086
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
PACKAGE MECHANICAL
Figure 38. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
1 48
e
D1
B
24
25
L1 A2 A
E1 E
DIE
A1 C CP
L
TSOP-G
Note: Drawing is not to scale.
Table 26. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
Symbol Typ A A1 A2 B C CP D1 E E1 e L L1 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 - 0.500 0.100 1.000 0.220 0.050 0.950 0.170 0.100 Min Max 1.200 0.150 1.050 0.270 0.210 0.080 12.100 20.200 18.500 - 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 - 0.0197 0.0276 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ
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sehcni
Min
sretemillim
Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0031 0.4764 0.7953 0.7283
NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 39. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline
D2 FD1 FD D1 SD
e
e E E2 E1
SE ddd
BALL "A1"
FE1 FE
e
b
A A1
A2
BGA-Z67
Note: Drawing is not to scale
Table 27. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE 12.00 5.60 8.80 0.80 2.75 1.15 3.20 1.60 0.40 0.40 - - 11.90 0.45 9.50 4.00 7.20 0.10 12.10 0.4724 0.2205 0.3465 0.0315 0.1083 0.0453 0.1260 0.0630 0.0157 0.0157 - - 0.4685 0.40 9.40 0.25 0.70 0.50 9.60 0.0177 0.3740 0.1575 0.2835 0.0039 0.4764 0.0157 0.3701 Min Max 1.05 0.0098 0.0276 0.0197 0.3780 Typ Min Max 0.0413 inches
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 40. TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline
D D2 FD1 FD D1 SD
e
e E E2 E1
SE ddd
BALL "A1"
FE1 FE
e
b
A A1
A2
BGA-Z67
Note: Drawing is not to scale
Table 28. TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
Symbol A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE 12.00 5.60 8.80 0.80 2.75 1.15 3.20 1.60 0.40 0.40 - - 11.90 0.80 0.45 9.50 4.00 7.20 0.10 12.10 0.4724 0.2205 0.3465 0.0315 0.1083 0.0453 0.1260 0.0630 0.0157 0.0157 - - 0.4685 0.40 9.40 0.50 9.60 0.25 0.0315 0.0177 0.3740 0.1575 0.2835 0.0039 0.4764 0.0157 0.3701 0.0197 0.3780 millimeters Typ Min Max 1.20 0.0098 Typ inches Min Max 0.0472
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
PART NUMBERING
Table 29. Ordering Information Scheme
Example: Device Type NAND Flash Memory Density 01G = 1Gb 02G = 2Gb 04G = 4Gb 08G = 8Gb Operating Voltage R = VDD = 1.7 to 1.95V W = VDD = 2.7 to 3.6V Bus Width 3 = x8 4 = x16 Family Identifier B = 2112 Bytes/ 1056 Word Page Device Options 2 = Chip Enable Don't Care Enabled Product Version A = First Version B= Second Version C= Third Version Package N = TSOP48 12 x 20mm (all devices) ZA = VFBGA63 9.5 x 12 x 1mm, 0.8mm pitch (1Gb devices) ZB = TFBGA63 9.5 x 12 x 1.2mm, 0.8mm pitch (2Gb Dual Die devices) Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option blank = Standard Packing T = Tape & Reel Packing E = Lead Free Package, Standard Packing F = Lead Free Package, Tape & Reel Packing NAND02GR3B 2 A ZA 1 T
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to '1'. For further information on any aspect of this device, please contact your nearest ST Sales Office.
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REVISION HISTORY
Table 30. Document Revision History
Date 25-Feb-2005 Version 1 First Issue Automatic Page 0 Read feature removed throughout document. LFBGA63 package removed throughout document. Data Protection section and Figure 23., Equivalent Testing Circuit for AC Characteristics Measurement added. TFBGA63 and VFBGA63 packages updated. Note added to Figure 4., TSOP48 Connections, x8 devices and Figure 5., TSOP48 Connections, x16 devices regarding the USOP package. Write Enable (W)., Table 11., Table 12., Table 14., Block Lock Status, Figure 19., Table 20., Table 22., Table 23., Table 25. and Table 30. modified. 512 device and USOP package removed throughout document. Figure 4., Figure 5., Table 22., Table 23. and Copy Back Program modified. Revision Details
16-Aug-2005
2
18-Oct-2005
3
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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